1. Field of the Invention
The present invention relates to a circuit with an improved transmission scheme, and more particularly to a circuit for reducing the transmission delay of redundancy evaluation of the synchronous DRAM (SDRAM).
2. Description of the Prior Art
Many kinds of electrical products are invented each day, and these new products usually need a higher processing speed than before. A key point for upgrading the processing speed is to effectively improve the access time from data storage, such as decreasing the transmission delay of the DRAM (Dynamic Random Access Memory) or of the SDRAM. In the present day, chip yield on the processed silicon wafer becomes an important topic when electronic devices are mass produced today. One typical evaluation for the chip yield is done with replacement of defective circuit elements. For example, redundant cells are inevitable in DRAM for replacing defective memory cells that are identified in an electrical test after wafer processing. However, the conventional scheme usually causes a significant delay due to identifying whether a redundant memory cell is used. This disadvantage turns out to be critical particularly for high-speed SDRAM design.
Referring to FIG. 1, which represents a block diagram illustrative of the conventional column redundancy scheme of the SDRAM circuit, an external address from an address buffer 101 is firstly decoded and is then routed to the global column factor generator 103. Accompanied with a column address strobe pulse (CASP) and a column burst pulse (COL.sub.-- BURST) that passes through a NOR gate 102, the global column factor generator 103 generates a plurality of global column factors. The global column factors ("CF" for short hereinafter) are then directed to a local factor generator 105 that also generates several local column factors for controlling bit-line selector (YS) of several memory blocks (such as 4 or 8 blocks). On the other hand, the global column factors are also directed to a column redundancy check 104 for evaluating whether a redundant memory cell is needed when a column synchronous pulse (YPULSE) comes up. The column redundancy check 104 enables a normal column path enable signal (CYEN) to indicate that a normal memory cell is accessed. In other words, the column redundancy check 104 enables a redundancy column path enable signal (CRYEN) to indicate that a column redundant cell is used. Finally, the local CF generator 105 generates a normal bit-line selector (YS) or a redundancy bit-line selector (YSR) to enable a read/write operation to the SDRAM according to the CYEN and CRYEN. Clearly, the redundancy evaluation will not be performed until the global factors arrive at the column redundancy check 104.
FIG. 5 describes a waveform diagram illustrative of when an external address and a system clock (SYS.sub.-- CLK) come to drive a read/write operation in the SDRAM circuit of the FIG. 1. Obviously, the CASP, the global CF, and the YPULSE appearing later than the SYS.sub.-- CLK will start a memory read/write operation. A duration to perform a redundancy evaluation is indicated by .tau., which is conventionally about 1.about.2 nanoseconds. This is an unacceptable value, especially for those high operation circuits. A need has therefore arisen to disclose a circuit, in which the transmission delay of column redundancy used in the SDRAM can be significantly reduced for achieving the requirement of high operation speed.